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Senior Design Engineer

162175
San Jose, CA, United States
Jan 7, 2022

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx is a US federal government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employee's work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination or have an approved accommodation by December 8, 2021.

The Xilinx Central Engineering Memory Subsystem team is searching for a passionate, adaptable and innovative design engineer to contribute towards the next generation of HBM PHY and more.

Xilinx has an opening for a Senior Hardware Design Engineer in the IP Design team. This position entails working on digital IC design development of PHY and integration of Memory subsystem blocks for next generation FPGAs. Candidate will support varied aspects of the entire design process including RTL design and functional verification, FE design flows and/or synthesis, timing closure, supporting SW views and working with test engineers on silicon verification and characterization.

Job Description

  • The candidate will be responsible for different design stages in the RTL to GDS implementation.
  • The candidate will design, implementation RTL for complex digital and analog blocks using Verilog/System Verilog.
  • The candidate will be responsible for physical design flows (synthesis with DFT) and work on Static Timing Analysis.
  • The candidate will work closely with Functional Verification teams to support block level verification (constrained-random and/or directed verification environments using System Verilog and UVM).
  • The candidate is expected to have strong scripting skills in Perl, Tcl, Shell and/or other languages to support existing & develop new design automation tools/flows for the varied aspects of the design implementation.
  • The candidate is expected to work with various design groups across different disciplines in different geographical locations.
  • The candidate is expected to have regular communication with project teams worldwide to resolve issues and ensure targeted goals.

 

Job Requirements

  • BS with 3+ or MS with 1+ or PhD in Electrical Engineering, Computer Engineering or related equivalent
  • RTL design implementation of Digital blocks using Verilog/System Verilog.
  • Knowledge in VLSI design, Design Automation, IC design.
  • Basic knowledge of EDA Tools (like Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso).
  • Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis is preferred.
  • Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred.
  • Basic understanding of FPGA architecture and customer usage model is a plus.
  • Knowledge of Cadence SPICE, IC compiler is a plus.
  • Experience with Silicon debug/validation at the tested and board level is a plus.
  • Proficiency in Perl, Tcl, Shell, Python and/or other scripting language.
  • Experience creating internal and/or customer facing detailed documentation.
  • Excellent written and verbal communication skills in English.
  • Self-motivated team worker with ability to work in a fast-paced work environment.

 

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