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Senior SoC RTL Engineer

162179
Hyderabad, India, India
Jan 10, 2022

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx Processing and multimedia SoC design group strive to get best in Industry class features and productize them. The job requires a candidate who is not limited by the boundary and willing to push the bar. The role of RTL designer is to develop and integrate Processing and Multimedia sub-system for state of the art 7nm SoC products. The successful candidate will own subsystem/large IPs with multiple IP and interconnect including any custom SoC logic requirements. He/she should be thorough with std-cell based SoC design methodology and timing closure. The knowledge of video codec, image signa processing will be highly appreciated.

-The candidate should be fluent in Verilog and system Verilog

-should know timing closure practices in an SoC

-should have aptitude to learn new technology in processing system/multimedia

-should be aware of quick SoC integration and quality checks like Lint

-Candidate should have good depth in CDC, RDC and other clock synchronization issues

-will be point of contact for the subsystem that he may own

Bachelors/Masters in Electrical engineering

Relevant experience : 5+ years

 

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