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Xilinx Processing and multimedia SoC design group strive to get best in Industry class features and productize them. The job requires a candidate who is not limited by the boundary and willing to push the bar. The role of RTL designer is to develop and integrate Processing and Multimedia sub-system for state of the art 7nm SoC products. The successful candidate will own subsystem/large IPs with multiple IP and interconnect including any custom SoC logic requirements. He/she should be thorough with std-cell based SoC design methodology and timing closure. The knowledge of video codec, image signa processing will be highly appreciated.
-The candidate should be fluent in Verilog and system Verilog
-should know timing closure practices in an SoC
-should have aptitude to learn new technology in processing system/multimedia
-should be aware of quick SoC integration and quality checks like Lint
-Candidate should have good depth in CDC, RDC and other clock synchronization issues
-will be point of contact for the subsystem that he may own
Bachelors/Masters in Electrical engineering
Relevant experience : 5+ years