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Senior Design Verification Engineer

162042
San Jose, CA, United States
Dec 14, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve everyday problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Description

Xilinx Central Products Group (CPG) is looking for a Senior Design Verification Engineer, who can provide technical leadership and contribution on high speed Memory Controller IP verification.

The individual will help architect, develop and use simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, LPDDR, HBM, RLD, and QDR, Memory Controller IP designs.

Your experience and expertise in developing advance SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved quality and execution of Xilinx’s devices.

The individual will also collaborate with Architecture, Design, and Software teams to prove that the system-level architecture requirements are met as part of Pre-Si Functional Verification.

Work includes Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs.

 

#mh

 

Job Qualifications

  • BS with 5+ years of exp MS with 3+ years of exp or PhD in Electrical Engineering, Computer Engineering or related equivalent
  • Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.
  • The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on Memory Controllers (DDR, LPDDR, HBM, RLDRAM, QDR), high performance IPs and/or SOC designs.
  • Require hands on experience with verification of state-of-the-art memory controllers such as DDR, LPDDR, HBM, RLDRAM and QDR. Requires strong understanding of current memory controller protocols and calibration (DDR3/4/5, LPDDR3/4/5, RLDRAM3, QDR2, QDRIV, HBM-Gen1/2/3), JEDEC specification, board skew and jitter modeling.
  • Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs
  • Require experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
  • Require strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus. 
  • Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
  • Experience with FPGA programming and software is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
  • Experience with gate-level simulation, power verification, reset verification, contention checking is a plus.
  • Experience with silicon debug at the tester and board level, is a plus.

 

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