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Xilinx SERDES team develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. We are seeking a SERDES physical layer (PHY) design engineer to join our world-class team. The job responsibilities include the following:
- RTL design of digital blocks such as calibration loops, clock-and-data recovery (CDR), equalization adaptation loops, and digital signal processing (DSP) block
- Working with system architecture, verification, DFT, timing, PnR, and validation teams to perform pre-TO design sign-off and to bring up silicon
- Micro-architecture: contribute or lead to deliver power and area efficient implementations of required silicon functionality
This position requires M.S. in electrical engineering, computer engineering, or closely related fields, with relevant project/internship experience.
Successful candidates need to demonstrate the following
- Project/internship/work experience in implementing digital blocks through RTL design, preferably having completed at least one cycle of Synthesis and Place-and-Route of a digital circuit block.
- Strong teamwork and communication skills