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Sr Staff Design Engineer

161883
Singapore, Singapore, Singapore
Nov 23, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

  • Architect next generation verification environment.
  • Applies advanced understanding of verification methods, tools, and typical challenges to promote best practices in component verification and integration (e.g., metrics-driven formal verification methods, automated integration)
  • Develop and drive verification architecture and methodology
  • Creates verification plans at the system level
  • Mentors team members in verification testing and the appropriate exercising of component innovations and/or the functionality desired by customers
  • Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications in a timely manner
  • Reviews test plans and work with verification engineers to design test methodologies that ensure the achievement of block quality

The successful candidate should possess/be at minimum

At least 8 years of hands on verification experience with SystemVerilog/OVM/UVM

Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering

Proficient in developing scripts with Perl and Python

Strong understanding of verification process from test plan to coverage completion

Strong communication and Analytical skills

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