The Product Engineer position is in the Software & AI Products group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP Compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve FPGA compilation software quality of results and ease of use in order to enable the next generation of designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties:
Deep dive on new and critical tool issues seen by Vivado users internally and externally to identify workarounds and future enhancements. Drive critical customer escalations to closure and contribute to new technologies rollout.
Contribute to triaging reported issues in several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively.
Actively explore innovative methodologies and their impact on flow and design practices, with emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family.
Work closely with Xilinx Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience.
Develop and deliver training materials on new features and methodologies.
Stay current with and propose the internal use of industry approaches, algorithms, and practices
Education and Experience Requirements
MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience.
Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations.
Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired.
Design Enablement: Has good understanding of design methodologies for timing closure and compile time reduction.
Problem Solving: Ability to handle and solve complex system level issues.
Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner.
Teamwork: Able to work with several teams across sites and domains with a positive attitude under variable workloads.