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Senior HLS Backend Engineer

161724
Beijing Shi, China, China
Nov 5, 2021

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Job Description

Description

Xilinx Beijing R&D center is the core team for developing the Vitis High-Level Synthesis (HLS) tool. This tool transforms a C specification(C, C++, SystemC and OpenCL) into a RTL implementation that can be synthesized into a Xilinx FPGA. It improves the productivity for hardware designers by enabling them working at a higher level of abstraction while creating high-performance hardware. It also help improves system performance for software designers as they can accelerate the computation intensive parts of their algorithms on a new compilation target, the FPGA. Specifically, the main responsibilities of this job are:

  • Define the architecture for the hardware design automatically generated from high level synthesis tool.
  • Develop software algorithms for automatically generating the hardware design in high level synthesis tool.

 

 

  • Degree of M.S or Ph.D in computer science or electrical engineering.
  • Design/implementation skills in Verilog/VHDL.
  • Experience on C++ programing.
  • Good learning competency and self-motivated
  • Fluent English
  • Experiences on HLS/Compiler/EDA tool development is preferred.
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