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Staff Timing Engineer

161624
San Jose, CA, United States
Nov 15, 2021

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Job Description

Description

Xilinx is seeking a Staff SDC timing engineer to develop SDC timing constraints for large SOC’s with multiple physical blocks and 300+ clock domains. The candidate will be responsible for running pre-route timing QC and QoR regressions and resolving SDC issues in the pre-route and post-route implementation.  He/She will also support the RTL design team in the RTL handoff process by running additional QC regressions including LINT, DFT DRC, CDC, RDC, CLP, and Fishtail.  The candidate will be responsible for driving content owners and managing the overall RTL dashboard cleanup for each RTL handoff milestone.

 

The position requires a mix of SDC knowledge, EDA tool competence and TCL-based scripting capability (both in EDA tool environments and stand-alone Linux TCL shell scripts).  Ideal candidates will not only have extensive SDC development and debug experience, but, also have experience cleaning various RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.  As a middle end engineer, familiarity with both front end (RTL) flows and backend (Synthesis and P&R) flows is desired. 

High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits are encouraged to apply.

Experience with the following is required:

  • Synopsys: Design Compiler (Logic Synthesis)
  • Synopsys: Primetime (STA)

Experience with any of the following is desired:

  • Synopsys: Spyglass RTL LINT
  • Synopsys: Spyglass RTL DFT
  • Mentor: Questa CDC (Zero In)
  • Mentor: Questa RDC
  • Cadence: Conformal Low Power
  • Fishtail: Confirm

Shell Scripting Experience:

  • Proficient with scripting languages TCL, Perl, Python, CSH
  • Proficient with Cron and LSF job control automation

 

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Experience and Education:

  • BS with 8+ years of exp or MS with 6+ years of exp or PhD with 3+ years of exp in Electrical Engineering or Computer Engineering or related equivalent 

Xilinx is a US federal government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employee’s work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination or have an approved accommodation by December 8, 2021.

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