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Senior DSP Design Engineer

161529
Hyderabad, India, India
Nov 2, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description 

Xilinx is looking for a talented individual to join the DFE Technology team in the position of Sr DSP Design Engineer. This team develops high performance and low cost digital front end (DFE) Radio designs for 5G base stations and DOCSIS Remote-PHY applications with Xilinx’s unique RFSoC and Versal products and influences future device architectures. As Sr. DSP Design Engineer, you will have the opportunity to work on, architect Wireless/Wired Communication embedded systems and develop building blocks required for Digital Front End for these Communication systems.

Key Responsibilities: 

  • Design and Implement DSP blocks related to Digital front end for 4G/5G base-stations.   
  • Responsible for design, optimization and testing of communication signal processing algorithms and its fixed precision implementation and test with matlab, embedded C/C++ and HDL on Xilinx devices.
  • Execute module level and system level verification/validation of DSP blocks. Develop test plan to get functional and code coverage.
  • Work within the team to define detailed design requirements, as well as providing FPGA based architectural expertise and guidance.
  • Work with geographically distributed teams, lead technical activities and obtain good understanding of dependencies to re-prioritize the tasks accordingly.
  • Candidate will participate in different phases of a project, including architecture, system design, coding, unit testing, integration and maintenance and customer support
  •  Responsible for writing Matlab based test scenarios to configure and analyze DSP block’s performance on FPGA evaluation platform
  •  Develops innovative but practical solutions to advanced technical problems in engineering.         
  • Create internal and external facing detailed documentation (micro-architecture design documents, test specifications, test reports, user guides, etc.). 

Technical Skill Requirements: 

  • Master’s/Bachelor’s degree in Electronics and Communication Engineering or equivalent preferred.
  • 10+ years of implementing DSP designs in wireless/wired Communication Systems.
  • 5+ years of hands on experience developing Communication systems on FPGAs.
  • 5+ years of hands on experience implementing performance optimized, fixed-point optimized and resource optimized DSP blocks.   
  • Strong understanding of signal processing algorithms and hands on experience in developing viable and optimized solutions for Wired/Wireless communication systems.  
  • Hands on experience in designing and implementing Digital Signal Processing blocks using VHDL/Verilog. Ability to translate a software model into fixed point hardware implementation.
  • Experience with coding signal processing kernels on DSP processors and/or SIMD and VLIW processor architectures is a plus.
  • Must have strong competency in simulating complex communication and signal processing algorithms.
  • Excellent understanding of cellular systems building blocks, with focus on LTE and 5G. Experience in integrating these building blocks is required.
  • Practical experience with designing the 5G wireless solutions a definite plus.
  • Deep understanding of wireless systems performance and features impact/trade-offs.
  • Experience in validation with Emulators and FPGA evaluation boards is highly desirable.
  • Understanding of data interfacing protocols eCPRI, AXI-Stream, AXI etc is desirable. 
  • Demonstrable proficiency with scripting language like Perl/Python/Tcl is required.
  • Understanding of formal verification/assertions, LINT and CDC tool is desirable.
  • Excellent documentation, presentation and communications skills.
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