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Sr System design

161453
Hyderabad, India, India
Oct 1, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

The candidate should have strong FPGA knowledge in Xilinx SoC products and its tool flows. The candidate should have extensively design, FPGA timing closure, system bring up and should have strong Vivado knowledge. 

Desired skills

  • Strong digital fundamentals
  • Verilog & System Verilog, debug capability
  • FPGA architecture, RTL design, implementation, FPGA timing constraints, STA and timing closure along with system bring up and debugs  
  • Proficient in Vivado/Vitis
  • Hands-on experience and well versed in scripting languages - tcl, Python
  • Knowledge and exposure of Xilinx SoC series of products – Zynq, Zynq MPSoC, Versal
  • Knowledge of PCIe, cache coherency protocols is a big plus
  • Able to operate independently

Education Requirements

BS/MS/ P.hd in CSE, ECE, EEE
Years of Experience

5-8 Years of experience

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