This exciting position in the Xilinx Data Center Storage IP and Solutions Engineering group as the RTL & System design lead will provide the individual with an opportunity to demonstrate strong technical leadership in Xilinx next generation Storage IP/Systems solutions Design. Join us in providing innovative IP/Systems solutions on our journey in developing world class IP/Systems solutions running on Xilinx All Programmable highly flexible and adaptive FPGA platforms.
As an RTL Design Lead you will work as part of a team responsible for IP/Systems design in the data center storage space. RTL Design Leads are expected to have thorough understanding of the Data Center Storage space, corresponding standards, participate in providng inputs during solution architecture, Micro-architecting, RTL Designing & developing IPs/Systems and as well as new product exploration, evaluating emerging technologies.
This position requires the individual to be creative, team-oriented, technology savvy, able to come up with real world use case scnearios for designing the solutions and ensure high quality & high performance solution delivery to customers
A major part of your responsibility will be to take a lead technical role in product/IP micro-architecture definition and RTL design in the Data Center Storage IP & System development including:
- Understanding product specifications and deriving the module level architecture
- Evaluating high level architecture to a implementation feasibility level
- Derive the product metrics (performance, latency etc.) & ensuring micro-architecture to ensure the performance requirement
- Defining u-Architecture, designing, documentation, prototyping - Interact with internal stakeholder teams as necessary
- Evaluating and executing design and development plans for IPs
- Working with cross functional teams in reviewing the verification and validation plans and ensure the product delivered is of high quality
- Contributing to process improvement in design and development methodologies that impact the productivity
- Providing feedback to next generation system architecture
- Proficiency in RTL coding and RTL methodologies
- Strong oral and written communication skills are essential
- Ability to work collaboratively with other engineers and have good influencing and leadership skills
- Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces like Storage IPs/Solutions, PCIe, Ethernet
- Good understanding of system design aspects and its impact on performance and throughput
- Experience in system level verification, validation and debugging of system solutions
- Familiarity with electrical challenges that come with high speed link design & testing on-board
- Detailed knowledge of storage, networking and Ethernet protocols is a plus
- Experience with high speed link validation above 10Gbps line rate is a plus
- The ideal candidate should be a proactive contributor and subject matter expert
- Ability to effectively communicate with customers about existing and new product directions and technology.
- Individual must work effectively with Director and Senior Director level employees within the function, across functions and with external parties.
- To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups.
- Contributes, explicitly or by example, to the standards and processes used by Xilinx or product development.
Education and Experience
- A minimum of 8 years of relevant experience is required.
- A Bachelor of Science Degree in Electrical Engineering or Computer Science, a Master Degree or equivalent experience is required.
- Demonstrated ability to have completed multiple, complex technical projects.
- Demonstrated ability to provide technical advice, leadership, and direction to more junior engineers.
Desirable key areas of expertise:
- NVMe, RDMA based IP/product development
- PCIe based IP/product development