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Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
Xilinx is seeking a capable and motivated RTL/ASIC design manager to lead front end design team of next generation AI Engine. You will take part in project planning and execution of silicon design of high-performance, low-power processor and accelerator IP for AI/ML applications.
-Manage front end design team to execute on design and implementation of AI/ML accelerator/processor
-Drive key metrics and milestones to meet silicon tapeout schedule
-Review micro-architecture and design to meet architecture spec and optimize power, performance and cost
-Adapt and adjust to evolving requirements with creative and practical decisions
-Drive interaction and collaboration with architecture, verificaton and physical design teams to achieve high quality design
Masters with 3+ years of working experience in the above areas.