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Thorough understanding of complete ASIC timing closure flow with strong STA fundamentals.
Must have gone through multiple SoC tape-out experiences including Timing and Functional ECO cycles.
Expertise with industry-standard STA tools like Primetime, PT based TCL scripting is a must
Should have prior experience with block and full-chip constraints development and providing guidance to RTL and PD teams to help meet the timing spec
Should understand the complete physical design aspects/stages related to timing closure.
Hands-on with PnR on few blocks would be helpful.
Good understanding of physical closure, floor plan, CTS, routing, timing, noise, crosstalk, electromigration, IR drop, process variations, characterization, 3D ICs, low power CMOS, digital logic, and circuit design, ASIC/ SOC integration.
After initial flow/methodology ramp-up should be able to operate independently and drive issues to closure working with cross-site and cross-functional teams.
Should be able to drive new flows/methodologies deployment efforts/activities
Good verbal and written communication skills are a must.
Should be a very good team player and be able to guide junior engineers on day-to-day issues/problems.
Any experience with technical management would be an added plus.
5 - 8 years of relevant experience.
Education à ECE/EE Engineering background, Specialization in VLSI/Semiconductors/Micro-electronics is added plus.