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Xilinx’s production verification team is responsible for developing state-of-the-art test solutions for FPGAs, 3D-ICs, Programmable SoCs, and ACAPs. We are looking for a talented, self-driven and motivated engineer to join our team of experienced and accomplished engineers.
As a DFT Engineer, you will be working with cutting-edge Xilinx devices, including next generation ACAPs. Based on TSMC’s 7nm technology, ACAPs are ideally suited to accelerate a broad set of applications in the emerging era of 5G, big data and artificial intelligence. As part of test solutions development, you will be using Xilinx industry leading Vivado Design Suite to develop RTL based test designs and Vitis Software Platform to develop diagnostic firmware for failure analysis.
In this position, you will have a unique and exciting opportunity to use your design, debug, and verification skills to test, verify and validate FPGA Fabric resources in Combinatorial-Logic-Blocks (CLBs), Interconnect Matrices, and High-Speed Clock Distribution Networks. You will architect and develop test methodologies and flows for testing Xilinx devices, and in return, you will gain valuable hands-on experiences as part of your career development.
Key responsibilities for this challenging and rewarding opportunity include but are not limited to the followings:
• Verify pre-silicon functional behaviors using RTL simulations
• Develop high coverage and cost effective DFT test methodologies
• Create and implement test plans in Automatic-Test-Equipment (ATE) test environments
• Debug test patterns and deliver robust and stable manufacturing test flows
• Analyze test coverages to achieve excellent out-going qualities for every device
• Develop diagnostic firmware using C code and running in on-chip embedded Microcontroller to root cause failing mechanisms and improve manufacturing yields
• Characterize post-silicon performance across test conditions using volume manufacturing test data
• Write custom automation tools to facilitate test developments and debug test failures.