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Design Engineer 2

161313
Hyderabad, India, India
Sep 15, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Description:

 

The product verification team is seeking a DFT engineer to join an exciting career on Scan, MBIST, iJTAG test development of the latest 7nm MPSoC (Multi-Processor System on Chip) products and beyond. The IPs range from ARM-based Processors to critical IPs which provide automotive, data center, machine learning, and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly inserted, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield, engineers to debug and root-cause failures/defects. You will also be creating an RTL design utilizing FPGA fabric resources to build communication logic for stimulus and response delivery between the device and ATE.

 

Key responsibilities include but are not limited to:

  • Work closely with design team and make sure DFT structures are correctly inserted.
  • Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
  • Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model
  • Responsible for debugging of pattern issues on bench/ATE to root cause the problem
  • Assist in Diagnosis and Yield enhancement through product lifecycle

 

 

Qualifications:

  • BS or MS in Electrical/Electronics/Computer Engineering
  • 3-5 years of experience as a DFT engineer
  • Experience in creating and implementing complex chip-level DFT architecture
  • Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
  • Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay), and scan compression.
  • Knowledge of MBIST is a plus.
  • Proficient in logic design using Verilog and experience in synthesis and STA
  • Experience in developing test benches and simulation in RTL/GATE/SDF environments
  • Knowledge of FPGA synthesis and design flow is a plus
  • Experience with post-silicon debug and bench setup is a plus
  • Good communication skills work well in a group environment that spans across continents
  • Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
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