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Senior Verification Engineer

161206
Hyderabad, India, India
Oct 28, 2021

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Job Description

Description

  • Experience with development of UVM, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify complex designs.
  • Strong Verification Fundamentals
  • Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
  • Experience with FPGA programming and software is a plus.
  • Verification Experience in DFT and embedded microcontrollers using 'C' tests.
  • Knowledge of protocols like AXI, JTAG
  • Experience with one of scripting language like perl, python.
  • Good Communication Skill

Education Requirements : B.Tech / M.Tech

Years of Experience : 10-15 years

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