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Staff Design Engineer - Circuit Design and Timing

161150
San Jose, CA, United States
Sep 9, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Description

Applicants should possess very good knowledge about circuit and layout design in the area of chip level CLK network distribution, should have very good understanding of Jitter, Skew, Noise and their impact on CLK and system level performance.

The successful candidate will be responsible for leading people from different groups for Design Implementation and verification to achieve the optimal result.  It will require a proactive candidate with a proven record of success in cross functional and cross site team environment. The candidate is expected to have working knowledge in the following area

 

#mh

 

Job Qualifications

  • BS w/ 8+ yrs or MS w/ 6+ yrs or PhD with 3+ year of experience in Electrical Engineering, Computer Engineering or related equivalent 
  • Top level block level implementation using combination of Custom design/layout entry tool like Virtuoso and Design compiler and Place and Route methodologies
  • Work closely with digital, analog, and physical design teams to optimize for performance, power, and area 
  • Timing closure of the block using combination of Spice and STA timing analysis tool like Prime Time
  • Assist in the validation and debug silicon products in support of release to production
  • Good inter personal skills and communication skills to be able to interact well with other members in the functional teams of the business unit.
  • Participate in development planning, dependencies and scheduling.
  • Assist in the validation and debug silicon products in support of release to production.
  • Experienced in automating flows. Good scripting skills (TCL/Perl/Python)

 

Preferred Requirements:

  • Knowledge of FPGA and Vivado tools
  • Interact with tool vendors and debug tool related or IP related issues independently.
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