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Successful candidates will work as part of an experienced team executing projects in advanced 7nm (FinFET) CMOS manufacturing processes. Layout is extremely challenging at these smaller process nodes. Project tasks will include layout of analog and digital circuits .There is also the opportunity to contribute to methodology initiatives to accelerate design layout.
• Strong foundation in layout design for mixed analog / digital ICs with 7nm CMOS process geometries experience
• Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage
• Extensive Floorplanning, power grid and signal flow planning experience
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Excellent understanding of signal and clock shielding and isolation techniques
• Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects
• Excellent written and oral communication skills are also required
• Ability to work well as part of a team
• Excellent problem solving skills
Bachelors Degree in Electronic and Electrical design or similar discipline