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Sr Design Engineer

161066
Hyderabad, India, India
Aug 31, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx is looking for a talented individual to join the high speed memory interfaces design engineering group, in the position of Senior Design Engineer to work on development of next generation highly configurable blocks that operate at over 1 GHz data rate.

 

The successful candidate will own design and implementation of complex blocks to meet functional, performance timing, area and power requirements. The area of focus will be on micro-architecture, RTL design, interaction with SoC architecture team, integration, linting, CDC checks, synthesis constraint development, and timing closure activities.

 

Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.

B.E/M.E/M.Tech or B.S/M.S in EE/CE with 6+ years of relevant experience

4+ years of experience in designing complex blocks of an SoC

Excellent Verilog and logic design concepts

Experience with sign off tools like DC/PT

Experience with automation using scripting techniques such as PERL, Python or TCL

Knowledge of bus protocols like AXI/AHB

Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, and ModelSim.

Excellent communication and problem solving skills.

Should have experience working in geographically dispersed team and should be a strong team player

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