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Xilinx is looking for a talented individual to join the high speed memory interfaces design engineering group, in the position of Senior Design Engineer to work on development of next generation highly configurable blocks that operate at over 1 GHz data rate.
The successful candidate will own design and implementation of complex blocks to meet functional, performance timing, area and power requirements. The area of focus will be on micro-architecture, RTL design, interaction with SoC architecture team, integration, linting, CDC checks, synthesis constraint development, and timing closure activities.
Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.
B.E/M.E/M.Tech or B.S/M.S in EE/CE with 6+ years of relevant experience
4+ years of experience in designing complex blocks of an SoC
Excellent Verilog and logic design concepts
Experience with sign off tools like DC/PT
Experience with automation using scripting techniques such as PERL, Python or TCL
Knowledge of bus protocols like AXI/AHB
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, and ModelSim.
Excellent communication and problem solving skills.
Should have experience working in geographically dispersed team and should be a strong team player