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This position is provided for Xilinx deep learning acceleration IP development, you will have the chance to build / verify and implement the acceleration IP with verilog RTL or AIE programming for state of the art deeplearning algrithms.
1. Degree of M.S or Ph.D in computer science / electronic engineering / micro-electronics.
2. More than 3 years’ experience on complex hardware logic design.
3. Strong design / implementation skills in Verilog.
4. Good learning competency and self-motivated
5. Fluent English
Preferred knowledge and experience:
1. Experience on computer architecture or micro-architecture design.
2. Experience on deep learning aligrithms or neural networks.
3. Experience on Xilinx AIE programming development.