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Standard Cell Library Design (1 Year Contract)

160983
Singapore
Sep 6, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Description:

  • Help automate and enhance standard cell design model generation and QA, including optimization required in mapping to new technology
  • Develop new checks to strengthen stdcell design QA checks
  • Participate in setting up and executing stdcell library design regression from RTL, QA to release
  • Perform spice based circuit checks for design robustness, and to validate performance change
  • Investigate and resolve block level design related issues

 

Education Requirement: BSEE/MSEE

Requirement: 

  • Minimum 3 years of standard cell or ASIC design experience.
  • Good understanding of library characterization tool Liberate and/or Silicon Smart
  • Knowledge of RTL Verilog, DFT modeling
  • Understanding of spice netlist and extracted DSPF formats
  • Familarity with common standard cell functionality
  • In-depth knowledge of timing Liberty format including Power, CCS, Variation Modeling
  • Understanding of various library design kit format and generation
  • Knowledge of device physics and process
  • Experience in Perl automation to qualify standard library design kits
  • Understanding of analysis and sign-off tools including LEC, Primetime
  • Knowledge of hspice and similar circuit simulators
  • Circuit design experience of state-of-the-art standard cells
  • Experience in Synthesis using Design Compiler and P&R using ICC2 or Innovus a plus
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