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Xilinx Central Products Group (CPG) is looking for a Senior Design Verification Engineer, who can provide technical leadership and contribution on high-speed Memory Controller IP verification.
The individual will help architect, develop and use simulation and/or formal-based verification environments, at block and full-chip FPGA level, to prove the functional correctness of DDR, LPDDR, HBM, RLD, and QDR, Memory Controller IP designs.
Your experience and expertise in developing advance SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved quality and execution of Xilinx’s devices.
The individual will also collaborate with Architecture, Design, and Software teams to prove that the system-level architecture requirements are met as part of Pre-Si Functional Verification.
Work includes Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs.
Xilinx is a US federal government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employee’s work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination or have an approved accommodation by December 8, 2021.