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Xilinx is looking for a developer with expertise in modeling complex HW architectures for fast simulation in SystemC TLM/C++ and development of supporting productivity tools.
As part of the Device Simulation Modeling team, the candidate will be responsible for the definition, development, validation and release of SystemC simulation models and related productivity tools for Xilinx’s All Programmable FPGAs, SoCs, 3D ICs and ACAP devices. Xilinx’s new hardware programmable SoC FPGAs and Adaptive Compute Acceleration Platform (ACAP) deliver most dynamic processor technology and are achieving record performances in Data Center, Wireless/5G, Automotive/ADAS and Emulation applications. These new applications and heterogeneous computing architecture brings in new challenges in simulation modeling, especially in fast simulation of large scale user designs that solve complex acceleration or AI/ML problems.
The position requires strong programming fundamentals in C++ and good understanding of System On Chip (SoC) hardware architecture.
• Bachelors in EE/CE/CS with 7 years or Masters in EE/CE/CS with 5 year of relevant experience
• Experience with software development C++
• Experience in object-oriented design and programming
• Self-sufficient and proficient in software development concepts and methods, coding, and debugging
• Experience with simulation modeling in SystemC TLM, UVM, Verilog or System Verilog
• Familiarity with hardware functional verification
• Proactively identifies and delivers solutions that reduce development and support costs
• Capable of developing a single project in its entirety
• Demonstrates technical flexibility and adaptability in developing in new and shifting software development and test environments
• Exposure to SoC performance analysis
• On-chip SoC protocols, such as AMBA or PCI-express
• Dynamic RAM (DDR/HBM) controllers and memory bandwidth optimization