UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

PHY/PLL RTL Design Engineer

160645
San Jose, CA, United States
Jun 10, 2021

Share:

Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Description

Be part of Xilinx’s IP team responsible for R&D/design of next generation clocking/PLLs solutions, next generation IOs, high speed memory (LPDDR4/DDR4, LPDDR5/DDR5, gDDR6, HBM2/HBM3, …), chip-to-chip Gbps proprietary PHY IP solutions. Responsibilities include but not limited to:

  1. Be part of the IP team of next generation PHY/PLL IPs. Engage in design and micro-architecture development phases
  2. Participate in macro defining specification, testing and verification of the IP components.
  3. Perform RTL-level design, including micro-architectural, of the digital portions of the IP architecture
  4. Work closely with methodology, PD teams to implement RTL design into GDSII.
  5. Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks
  6. Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.
  7. Generate and analyze  CDC, lint, synthesis, timing closure and DFT coverage reports 
  8. Influence the methodology on mixed signal IP flows on simulations, timing closure. Participate in establishing CAD and design methodologies for correct by construction designs.

 

#mh

 

 

Job Qualifications

  1. BS with 2+years of exp or MS in Electrical Engineer or Computer Engineering for related equivalent
  2. Experience working on PHY/PLL IP Design for high performance, low power FPGA/SOC designs
  3. Good knowledge of industry standards and practices in PHY/PLL Digital Design workflows and methodologies
  4. Some Familiarity with basic SoC Architecture, front-end SOC/Digital IPs design flows, including design, simulation, synthesis, and timing analysis/closure and sign-off.
  5. Demonstrated proficiency in Verilog and digital design.
  6. Expertise in some or all the following areas is beneficial:
    1. Experience in the design of digital circuits and components in RTL, building/own the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs. 
    2. Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc. 
    3. Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python.  work as part of design team on timing and functional fixes/ECOs
    4. Experience in cross interaction with verification, DFT and physical design teams. 
    5. DFT design and methodologies especially for Logic BIST.
  7. Good verbal, and interpersonal communication skills.
  8. Good written technical communications. Ability to produce technical documentation.
  9. Ability to work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast paste environment.
  10. Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge
Share:

Similar Jobs

Competitive Product Marketing

San Jose, CA, United States

Systems Design Engineer

San Jose, CA, United States

Senior Modeling and Tool Development Engineer

San Jose, CA, United States

PHY/PLL RTL Design Engineer

San Jose, CA, United States

Senior Software Engineer - Video/ML

San Jose, CA, United States

Senior Customer Operations Account Manager

San Jose, CA, United States

Global Campaign Manager

San Jose, CA, United States

Technical Program Manager- Software

San Jose, CA, United States

Research Engineer - Open Source

San Jose, CA, United States

RTL Timing Engineer

San Jose, CA, United States

SOC Design Engineer

San Jose, CA, United States

Senior Design Engineer

San Jose, CA, United States

Senior Design Engineer

San Jose, CA, United States

Senior Staff Design Verification Engineer

San Jose, CA, United States

Staff SOC Design Engineer

San Jose, CA, United States

Senior SoC Verification and Testing Engineer

San Jose, CA, United States

NPI Planning Intern/Co-op

San Jose, CA, United States

Data Center Silicon Product Manager

San Jose, CA, United States

SI/PI Design Engineer

San Jose, CA, United States

Staff System Design Engineer

San Jose, CA, United States

Route/Algorithms - Software Engineer

San Jose, CA, United States

Contractor - Senior Circuit Design Engineer

San Jose, CA, United States