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Be part of Xilinx’s IP team responsible for R&D/design of next generation clocking/PLLs solutions, next generation IOs, high speed memory (LPDDR4/DDR4, LPDDR5/DDR5, gDDR6, HBM2/HBM3, …), chip-to-chip Gbps proprietary PHY IP solutions. Responsibilities include but not limited to:
- Be part of the IP team of next generation PHY/PLL IPs. Engage in design and micro-architecture development phases
- Participate in macro defining specification, testing and verification of the IP components.
- Perform RTL-level design, including micro-architectural, of the digital portions of the IP architecture
- Work closely with methodology, PD teams to implement RTL design into GDSII.
- Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks
- Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.
- Generate and analyze CDC, lint, synthesis, timing closure and DFT coverage reports
- Influence the methodology on mixed signal IP flows on simulations, timing closure. Participate in establishing CAD and design methodologies for correct by construction designs.
- BS with 2+years of exp or MS in Electrical Engineer or Computer Engineering for related equivalent
- Experience working on PHY/PLL IP Design for high performance, low power FPGA/SOC designs
- Good knowledge of industry standards and practices in PHY/PLL Digital Design workflows and methodologies
- Some Familiarity with basic SoC Architecture, front-end SOC/Digital IPs design flows, including design, simulation, synthesis, and timing analysis/closure and sign-off.
- Demonstrated proficiency in Verilog and digital design.
- Expertise in some or all the following areas is beneficial:
- Experience in the design of digital circuits and components in RTL, building/own the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs.
- Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc.
- Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python. work as part of design team on timing and functional fixes/ECOs
- Experience in cross interaction with verification, DFT and physical design teams.
- DFT design and methodologies especially for Logic BIST.
- Good verbal, and interpersonal communication skills.
- Good written technical communications. Ability to produce technical documentation.
- Ability to work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast paste environment.
- Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge