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Area of focus: Senior Design Engineer – 2 (E6)
Be part of Xilinx’s analog/mixed signal IP design team responsible for the characterization and release of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, …) and chip-to-chip Gbps proprietary PHY IP solutions.
The candidate will
1) define and propose methodologies for next generation IP’s including flow automations.
2) Generate, validate and release various CAD views for AMS and digital designs of varying sizes and complexity.
3) work in a cross functional setup involving SOC, SW, CAD and PM teams in accomplishing various project milestones.
4) Ensure that IP databases are consistent and compliant with established quality using automated checks wherever possible.
5) Assist design and verification teams with appropriate and timely inputs from block characterization analysis
Requirements for this position include:
1) 8-10 years of experience in AMS IP packaging and release of different design views.
2) Functional understanding of different blocks in high-speed IO/PHY/PLL design to model them correctly.
3) Hands on experience in using various simulation tools such as Liberate-AMS, Primetime, Nanotime, HSPICE, Spectre etc.,
4) Ability to quickly ramp up on existing script-based Xilinx in-house methodologies and flows.
5) Ability to handle multiple IP’s at the same time and deliver with highest quality.
6) Strong scripting skills using languages such PERL, TCL, Python etc.,
7) Excellent written and verbal communication skills especially cross geographic interaction with overseas teams.
8) Exhibit strong initiative and ownership of tasks and responsibilities with an open mind to contribute to any area/project.
9) Good attitude towards problem solving.
Education Requirements: BTech or Equivalent
Years of Experience: 8-10yrs