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Xilinx is seeking a talented, motivated and self-driven RTL design engineer to be part of the Data Center Group (DCG) networking group. You will be taking part in design and implementation of high-performance networking designs and solutions, including those targeted for Xilinx 7nm ACAP.
JOB LEVEL CHARACTERISTICS
Having wide-ranging experience, uses professional concepts and company objectives to resolve complex issues in creative
and effective ways. Some barriers to entry exist at this level (e.g., dept/peer review).
Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises
judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own
area of expertise.
Determines methods and procedures on new assignments and may coordinate activities of other personnel (Team Lead).
MS in Electrical Engineering or Computer Engineering with a minimum of 3 years of related experience with a Bachelor's degree with 5 years or equivalent experience.
Requirements and skills
Strong knowledge in following
Experience in following is highly desired