At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
About team and this role
The hiring team's mission is to bridge the enormous capabilities of Xilinx FPGA to numerous software developers and companies. We have created and are working on the Vitis Libraries, which is a suite of open-source libraries for FPGA developed in high-level languages. The team consists of people of different backgrounds and has turned this diversity of backgrounds into advantages. Over just a few years, we have released hundreds of highly polished APIs in many domains and are striving to polish and cover more. In this role, you will develop advanced FPGA acceleration solutions and libraries, covering the full stack of both device programming and host scheduling and control using C++. Thanks to the HLS technology, no hardware description language will be needed, though we will gradually train you to design and express parallelism in FPGA and make best use of FPGA memory resources.
We expect sound knowledge/experience in at least one of the directions:
Heterogeneous computing (GPU, FPGA or ASIC accelerators; device programming or system scheduling),
Parallel program design (MPI, OMP, threads or co-routines).
Master or PhD degree in EE or CS, or
Master or PhD degree in other fields, with thesis projects strongly related software or digital circuit development.
Years of Experience
2 years for PhD or 4 years for master, in related position.