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Xilinx is looking for a talented, self-driven and motivated engineer to be part of our IP Verification team in Hyderabad. This exciting position in the Xilinx Wired IP Solutions Engineering group as Senior Verification Engineer-II will provide the individual with an opportunity to demonstrate technical leadership in verifying our next generation Ethernet and Interlaken solutions and also developing verification workflows and framework to test/verify IP's as delivered through Xilinx Vivado based IDE. Join us in developing Verification environment based on the industry standard UVM framework from scratch and drive high quality IP products that will be part of internal Xilinx Systems and high profile end customers.
As a Staff Verification Engineer / Verification Engineering Manager you will work as part of a team responsible for all phases of product development and are expected to engage with product development team in India and other Xilinx Development Centers (US/Canda), Architect testbenches from scratch, Evaluate best possible options to develop the testbench and implement, Execute the verification development life cycle through well-defined convergence metrics of coverage (Code, Functional and Assertions), achieve performance by automation techniques also by board validations of the high speed IP’s and ensure a high quality IP generated for customer use.
- B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 14 years of relevant experience in IP verification
- Prior experience in mentoring/leading/managing a team of at least 5 verification engineers
- Strong understanding and experience in verification of Ethernet protocols and IEEE 802.3 standards both MAC and PCS/PMA
- Knowledge on Ethernet protocols and standards like 1588, Pause, FEC, RSFEC, AN/LT, TSN and speeds from 1GE upto 100GE and beyond
- Knowledge on high speed serial transceiver GT and interface
- Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc
- Proven end to end verification of complex IP using System Verilog and latest methodologies which include UVM, OVM, VMM
- Proficient knowledge of System Verilog, HVL based methodology (UVM or OVM) and hands on scripting experience for automations
- Experience in verification including constrained-random, coverage driven verification environments
- Strong debugging, verification and board validation skills
- Should have handled verification of complex RTL designs by developing test cases and test benches including coverage analysis and validating them on the boards
- Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage
- Having System level knowledge / Verifying IP at system level will be a definite plus
- Self-driven, motivated, result oriented individual with superior academic achievements
- Excellent interpersonal, written, group communication and problem solving skills and very good team player
- Good organizational and execution skills with ability to multi-task and prioritize and able to work on deadlines with high quality deliverables