Senior Software Engineer I – System Modeling

Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve everyday problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on the work that matters - world-class technology that improves the way we live and work. We are ONEXILINX.

Xilinx System-Level Modeling and Tools team is looking for a talented and self-driven software engineer to work on Vivado and the Vitis family of software tools. Vivado is Xilinx’s primary environment that enables users to do end-to-end FPGA design. It is a revolutionary design environment built to accelerate the design and verification of our FPGAs, SoCs, and 3D ICs and is being extended to support the new ACAP devices. It is also the backbone on which the Vitis tools are built, which enable a wide variety of software and acceleration flows across many domains including DataCenter and embedded developers.

As a member of this high-performance team, the selected candidate will be responsible for extending the Xilinx Vivado and Vitis development environments to enable system-level simulation and virtual platform infrastructure, debug and profile of the design. The candidate will be working on simulation infrastructure and models for the next generation of Xilinx devices and methodologies. He or she will have the opportunity to interact with senior engineers across the globe, collaborate with them to introduce cutting-edge features critical for the next phase of company growth, especially keeping software developer requirements into consideration. The selected candidate will ensure that new features meet technical specifications and business goals and assume responsibility for the overall solution.  The candidate will be involved in all aspects of product development; design, prototyping, testing, and productization.

The team provides a fast-paced environment offering each of its member's immense opportunity to interact with a wide variety of people including from other organizations like hardware designers, marketing, support, and even direct customer interaction, and truly learn and grow their skills and capabilities.

• A minimum of Bachelors in EE, CS, CE with 5-6 years of relevant work experience.
• Experience in creating timing models using Accellera SystemC and TLM 2.0.
• Software development and debugging skills, fluency in C/C++ including OOP, data structures, and algorithms is required.
• Familiarity with hardware languages like VHDL, Verilog, and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is highly desired.
• Understanding of SoC architectures, Interconnects, NOC, memory, peripherals, etc is critical.
• Experience in at least one of the technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is desired.
• Experience in scripting languages like python, Perl is highly desired. Any knowledge of Tcl is a big plus.
• Basic understanding of device drivers, Linux drivers is desirable.
• Experience in software development environment on both Linux and Windows is desirable.
• Background in ASIC or FPGA design flow and general awareness of Electronic Design Automation (EDA) tools like synthesis, simulation, place and route is required.