Description - External
Xilinx Beijing R&D center is the core team for developing the Vitis High-Level Synthesis (HLS) tool. This tool transforms a C specification(C, C++, SystemC and OpenCL) into a RTL implementation that can be synthesized into a Xilinx FPGA. It improves the productivity for hardware designers by enabling them working at a higher level of abstraction while creating high-performance hardware. It also help improves system performance for software designers as they can accelerate the computation intensive parts of their algorithms on a new compilation target, the FPGA.
Specifically, the main responsibilities of this job are:
1) Define the architecture for the hardware design automatically generated from high level synthesis tool.
2) Develop software algorithms for automatically generating the hardware design in high level synthesis tool.
Requirements for this job including:
1) Degree of M.S or Ph.D in computer science or electrical engineering.
2) Design/implementation skills in Verilog/VHDL.
3) Experience on C++ programing.
4) Good learning competency and self-motivated
5) Fluent English
6) Experiences on HLS/Compiler/EDA tool developement is preferred.