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• Power integrity analysis for die package and PCB, which includes but not limited to layout extraction, electromagnetic and HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.
• Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain. Eye diagram and jitter analysis via Chip-package-board co-simulation.
• Optimal layer stackup & power plane assignment to minimize voltage noise.
• Special noise-sensitive power supply analysis and layout guideline.
• Signal trace length matching and impact to timing.
• Crosstalk analysis and reduction.
• Signal integrity and power integrity characterization and Lab measurement
• Full-wave simulation and model extraction for signal integrity and power integrity analysis.
BS with 8+ years of exp or MS 6+ years of exp or PhD 3+ years of exp in Electrical Engineering or Computer Engineering or related equivalent
• Solid background on transmission line theory and in-depth knowledge of electromagnetics, PCB layout and package layout techniques.
• Expertise with SI simulation tools, e.g. Synopsis HSPICE, Ansys HFSS, Q3D, Cadence PowerSI, PowerDC, and Agilent ADS.
• Hands-on expertise with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers.
• Experiences in high speed parallel interface signal integrity and power integrity, e.g. HBM2/HBM2e/DDR4/LPDDR4
• Experiences in Serdes signal integrity and power integrity, e.g. PCIe gen 4/gen 5, 100G Ethernet.
• Experiences in FPGA design is a plus.
• Self-motivated, teamwork, and good communication skills.