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We are looking for an FPGA Design Intern with an interest in designing innovative hardware solutions. As part of the Blockchain and Crypto team, the candidate will build an improved database design in hardware working closely with the CTO team.
The position requires knowledge of RTL or HLS design, familiarity with Vivado tools for HLS or RTL synthesis as well as place and route.
Experience with FPGA-based design, synthesis, place and route
• Experience with Xilinx Vivado tools
• Experience with creating and debugging RTL or HLS based designs
Preferred: Interest and experience in blockchain and cryptography
Minimum education level/experience: Student pursuing an Undergrad Degree in EE or a related field.