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DFT Engineer

160073
Singapore, Singapore, Singapore
Apr 12, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

The Product Verification team is looking for DFT Engineer (Entry Level) to join exciting career on Scan, MBIST and iJTAG test development of latest 7nm MPSoC (Multi Processor System on Chip) products and beyond. The candidate will work on complex SoC designs having ARM based Processor to critical IPs which provide automotive, data centre, machine learning and high-speed communication solutions

Key responsibilities include but are not limited to:

  • Deliver structural Test Patterns (Scan/MBIST/iJTAG) for multiple IPs in Next Generation Xilinx MPSoCs
  • Implement and verify DFT (Design For Test) schemes on hard-IPs in FPGAs
  • Implement techniques to test digital logic using Scan Compression, Stuck-at, Transition and Path-Delay fault models
  • Achieve target Structural Test Coverage of the logic, memories and Mixed-Signal IPs
  • Pre-Silicon and Post-Silicon verification of Test Patterns
  • Diagnose and debug the pattern failures on ATE to root cause the problem
  • Responsible for implementing techniques to Optimize Test Time, Dynamic IR drop in scan shift and Yield improvement
  • Work closely with Design Team and Product Engineering Teams to quickly resolve issues and meet high volume production schedule

  • Bachelor/Master’s degree in electrical/Electronic/Computer Engineering
  • 0-2 years’ experience in DFT and ATPG
  • Good understanding of Digital Design and ASIC design flow
  • Knowledge in VHDL/Verilog and IEEE 1149.1 standard
  • Basic understanding of VLSI testing / fault models / DFT
  • Knowledge of Perl / Shell Scripting is a plus
  • Knowledge of FPGA is a plus
  • Self-motivated and a strong team-player
  • Strong analytical and problem-solving skills
  • Ability to learn new tools and technologies
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