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Xilinx is looking for a talented individual to join the Wired IP Solutions Group (WISG) in the position of Staff ASIC/FPGA Design Verification Engineer. The successful candidate will join our design verification team developing ASIC and FPGA-based intellectual property (IP) to address the needs of state-of-the-art wired communications systems.
It is expected that the candidate will be an expert in Verilog coding and have in-depth knowledge or advanced verification methodologies such as constraint-random or UVM. Working knowledge of RTL design and processes would be an asset, as would experience with scripting languages such as Perl and TCL. It would also be desirable for applicants to have experience with wired communications protocols..
The successful candidate will have demonstrated their technical skill through extensive experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to architect innovative, high quality verification testbenches for complex IP products.
In addition to strong technical abilities, the position requires excellent written and verbal communication skills that will be utilized for multi-location collaboration, and developing verification specifications and test plans. A desire to mentor and coach junior engineers would be a plus.
We are building the next generation Internet. Xilinx already holds a leading position in the wired infrastructure manufacturing industry and is technologically well positioned to drive the ‘programmable imperative’ into all areas of advanced networking systems. This job opening presents an opportunity to work with a highly motivated team, best-in-class configurable silicon and software and industry leading wired communications technologies.