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Staff Verification Engineer

160049
San Jose, CA, United States
Jul 15, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

This is an exciting opportunity in IP Verification to work in a growing organization in Xilinx DataCenter Business Group . The candidate will have opportunity to work and develop on state-of-art UVM based verification environment on highly-configurable IPs designed towards datacenter performance and acceleration needs. This job will entail 

  • Verifying RTL implementation for complex digital blocks to ensure high quality
  • Developing verification strategies for new features, plan volume validation and coverage strategies
  • Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
  • Working with designers to do coverage analysis and take necessary actions to meet coverage goals
  • Integrate VIPs as needed
  • Closely work with design teams to drive feature enablement
  • Mentor junior engineers on the team

  • BS in EE/CE &  10+ years of experience, or an MS in EE/CE & 7+ years of experience
  • Knowledge of bus protocols like AXI/AHB.
  • PCIe, DMA and/or general CPU architecture knowledge preferred
  • Working experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/or BFMs is required
  • Strong understanding of simulation tools and knowledge of scripting languages like Perl, tcl or cshell
  • Highly motivated, Self-starter individual with ability to work in a fast-paced team environment

 

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