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Intern – FPGA Engineer – Data Center Group

Longmont, CO, United States
Feb 25, 2021


Job Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

We are looking for an FPGA Design Engineer Intern to join the Data Center Group (DCG) networking Group. You will be part of the team developing networking IP, platforms, applications, and solutions, including those targeted for the Xilinx SmartNIC solution. You will work closely with team members to perform various tasks depending on the stage of the project. Common responsibilities include, but are not limited to:

  • RTL level design and debug in Verilog / System Verilog, RTL level verification and debug in System Verilog / UVM
  • Integration of hardware, FPGA IP, firmware and software
  • Xilinx FPGA design, synthesis, implementation, timing analysis, design optimization
  • Hands-on work involving board bring-up, system debugging, and design validation over PCIe
  • Flow optimization and design analysis

Education Requirements

  • Minimum Junior pursing BSEE, student pursing MSEE
  • Duration of internship is full-time (40 hours per week) for 3 months
  • Start date: May/June 2021


Required Skills and Experience

  • Fundamental circuit design knowledge
  • Experience with RTL design, simulation, synthesis and implementation tools
  • Scripting (TCL/Python/Perl/etc), basic knowledge of Linux environment
  • Problem solving and debug skills

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