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Xilinx's Vivado Simulator is a full feature compile code simulator available to all Xilinx users. It supports all commonly used HDL languages including Verilog, VHDL, SystemVerilog, System-C and design that is developed mixing these languages. The simulator has full UVM support has TCL frontend, Waveform Viewer and integrated debugger.
Vivado Simulator currently has a TCL and C-APIs to control. As part of this project the Intern will develop a Python frontend for Vivado Simulator.
Roles and Responsibilities:
As a part of this role the candidate's responsibility includes
Looking for a candidate currently pursuing a M.S or Ph.D in CS/CE/EE with project work in Developing Python Libraries in C/C++.
Understanding of Hardware Description Language will be preferred.
This internship will be a minimum of 3 months to a maximum of 6 months, full-time (40 hours per week)
Expected start date is May/June 2021