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Software Engineer Intern-Simulator

159851
San Jose, CA, United States
Feb 9, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX

Xilinx's Vivado Simulator is a full feature compile code simulator available to all Xilinx users. It supports all commonly used HDL languages including Verilog, VHDL, System Verilog, System-C and design that is developed mixing these languages. The simulator has full UVM support has TCL frontend, Waveform Viewer and integrated debugger.

As part of refactoring and performance improvement the Simulator, it’s backend is being rewritten utilizing LLVM. The intern will work with a dedicated team to generate simulation Kernel for various Verilog/VHDL constructs using LLVM.

Roles and Responsibilities:

As a part of this role the candidate's responsibility includes

        • Interacting will all stakeholders and identify the HDL features he/she needs to translate to LLVM IR.
        • The candidate will be responsible for implementing the spaced feature in the backend. And work with the rest of the team to make sure it works correctly across different permutation of constructs.
        • The candidate will also be responsible for testing and fixes for the implemented features.

Education Requirements

Looking for a candidate currently pursuing a B.S, M.S or Ph.D. in CS/CE/EE with project work in Compiler using LLVM.

Understanding of Hardware Description Language will be preferred.

This internship will be a minimum of 3 months to a maximum of 6 months, full-time (40 hours per week)

Expected start date is May/June 2021

 

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