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This is an exciting opportunity to work in the Xilinx SOC Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on full chip, system level verification and support silicon bring up in the lab
-Create block level verification plan, test plans and subsystem test plan
-Develop block level test bench and tests in UVM methodology including scoreboard.
-Work on subsystem level verification
-Work with designers to get the coverage closure
-Port the block level tests to sub system test bench
-Integrate VIPs as needed
-Work with software, validation and emulation teams as needed.
-Work on other aspects of verification like CDC, gate simulation and formal verification
-Work on lab bring up as needed