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Looking for somebody to take ownership of CAD flows related to SOC-level chip construction. The ideal candidate should be comfortable with all stages of the chip design process -- including RTL, Netlisting, Construction (P&R and custom), Extraction, STA -- and should be comfortable debugging issues in any of those stages. For example, on any given day the candidate might be asked to trace pin mismatches in RTL, review design layout to root-cause broken parasitics in STA, and then run profiling on their perl & python scripts to optimize performance. The preferred candidate will also have some experience with design work to ensure robust debug skills.
Since this is a CAD role, the candidate must be comfortable with object-oriented programming and scripting languages. Both Perl and Python are required for this role, with greater emphasis on Perl for most tasks.
Finally, the candidate should be able to communicate effectively in a cross-functional role, possess strong organizational skills, and have a strong sense of teamwork. They should be enthusiastic about attacking a new problem every day and shouldn't be afraid of learning from each experience!
Job duties may include (but are not limited to):
MS in Electrical Engineering
Years of Experience