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Qualifications - External
The verification team at Xilinx is looking for a Staff Design Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs.
Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specification
Interact with architects and design engineers to create a comprehensive verification testplan
Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
Special Qualifications: Must have at least 1 year of prior work experience in each of the following: