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Senior Package Design Engineer 1

159321
Hyderabad, India, India
Nov 6, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Master’s/Bachelor’s Degree in Electrical/Electronic engineering with 7-11 years of experience in package design and layout of advanced and heterogeneous packages to meet/exceed package and system electrical and thermal performances. Successful candidate would be responsible to develop new package solutions including pin-out definitions, DRD/DFM and stack-up requirements. You should also be well versed with chip-package design flow and LVS verification. This job requires excellent communication, teamwork and strong problem solving skills. You will be part of the fullchip integration team in Hyderabad, responsible for driving integration of advanced process node chiplets using InFO technology.

 

Job Requirements:

  • Experience in CADENCE Allegro Package Designer, including constraints setup
  • Familiarity with AutoCAD, Gerber/ODB++/GDSII conversion software, and DFM tools
  • Strong knowledge in packaging substrate structures and manufacturing
  • Knowledge in 2.5D/3D, flipchip, WLP and wirebond assembly and reliability
  • Knowledge in SPICE, signal/power integrity, DDR3/4, and SerDes channel modeling for high speed design
  • Strong problem solving & excellent communication skills.
  • Exposure and interest in InFO package design and IC design flows are desired.

Education Requirements
B.Tech/M.Tech
 

Years of Experience

7 to 11 years

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