Job Description
Description
At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
Xilinx has an opening for a Senior Hardware Design Engineer in the SOC Design team. This team is responsible for designing the Processor Sub-system for the Adaptable Compute Acceleration Platform (ACAP).
In this highly visible role, you will:
- Own the design and implementation of blocks to meet functional, timing, area and power requirements. This entails:
- Driving crystallization of requirements
- Contribute to project planning by performing Scope/Schedule/Resources tradeoffs
- Author quality Microarchitecture Documents and conduct reviews
- Guide and review verification plans for these blocks
- Author RTL meeting company guidelines and follow up with timing constraints
- Design and implement logic functions that enable efficient test and debug
- React to changes in scope or dependencies in compliance with the project management methodology in effect to keep overall project on track
- Perform Functional Safety Analysis (FMEA, FMEDA) for blocks owned
- Participate in reviews of design/documentation/quality-metrics of peer blocks to ensure high quality deliverables
- Participate in silicon bring-up for features owned
- Specify and Implement Automation to increase design team efficiency
- Participate in build management
Required Qualifications
- MSEE (or equivalent) with 5 years of experience or BSEE (or equivalent) with 7 years of experience
- Atleast 3 years of RTL Design experience related to Arm based SOC Design
- Excellent verbal and written communication skills
- Excellent organizational skills and attention to detail
- Experience executing in parallel projects with rigid schedules
- Understanding of ARM architecture and AMBA Protocols such as APB, AXI, ACE and CHI
- Experience designing with multiple power domains including writing UPF
- Experience in designing blocks for an SOC
- Experience in integrating ASIC IP into SOC
- Experience with automation using scripting techniques such as PERL, Python or TCL
- Simulation experience and experience building basic block level verification suites
- Experience with synthesis, static timing constraints, analysis & optimization
- Ability to develop clear and concise engineering documentation
- Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
Desired Qualifications
- MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
- Experience with FMEA and FMEDA
- Working in design teams distributed over multiple sites
- Working knowledge of Cache Coherency protocols
- Post-silicon validation and debug experience
- FPGA knowledge and emulation experience
- Experience with Xilinx ISE or Vivado Design Suite
