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Senior Design Engineer 1

159289
Hyderabad, India, India
Jan 25, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

JOB Description:

• Ownership Synthesis and Static timing analysis of  Large subsystem , hierarchical and full chip designs
• Interact closely with Design, DFX and Physical Design teams for understanding dependencies, providing feedback and alignment deliveries
• Debug Synthesis, Timing QOR, SDC, Low power, Scan stitching issue
• Deliver Timing Closed database for Tapeout including Noise, Signoff Checklists , Functional/ Timing ECOs
• Create new and/or enhance synthesis/timing methodologies and develop proof of concept testcases, automate and work with CAD to roll out flows

Job requirements:

• Should be an Expert with hands on experience in full chip / Subsystem /IP timing closure, Low Power Synthesis, constraints development
• Must have knowledge on RTL/design understanding , Synthesis optimization, SDC, clocking, low power (UPF) and DFT
• Must have good understanding for ASIC physical design flows, with various tools , understanding and  scripting experience
• Must have strong debugging skills- timing issues, SDC , clock propagation
• Experience with developing flows, methodologies, jitter, spice simulation is a plus
• Must Worked on multiple tapeouts and projects directly responsible for  timing signoff

Education Requirements
BE / MS +


Years of Experience

5+ years

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