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Layout IC Design Engineer

Cork, Ireland, Ireland
Nov 23, 2020


Job Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX

Job Description:

The Serial Transceiver Group team designs high speed serial interface systems which are integrated into FPGA devices. These devices are used in a variety of applications such as automotive, wireline and wireless communications. Successful physical implementation of these serial communications solutions requires an advanced knowledge of mixed signal layout techniques. 

Successful candidates will work as part of an experienced team executing projects in advanced FinFET technologies at  16nm and 7nm CMOS manufacturing processes. Layout is extremely challenging at these smaller process nodes.

Project tasks will include: layout of analog and digital circuits; There is also the opportunity to contribute to methodology initiatives to accelerate design layout.





Job Requirements;

  • Knowledge of layout effects and best layout practices
  • Experience of block level floorplanning.
  • Ability to understand Design Rules, minimization of parasitic effects, IR drop and Isolation techniques.
  • Experience of Matching / Interdigitation techniques.
  • Good problem solving skills
  • Excellent written and oral communication skills
  • Good interpersonal/teamwork skills
  • Experience of layout on advanced nodes(28nm and below) is a preference
  • Exposure to industry standard IC layout entry and physical verification tools
  • Knowledge of Skill programming language a benefit
  • Keen interest in improving layout methodology
  • Experience of Cadence Virtuoso is preferred.

Education Requirements

  • Minimum education level/Experience: BS/BEng(Hons) 

Years of Experience

  • Minimum 2 years of layout experience