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STA EMIR Methodology Engineer

159253
San Jose, CA, United States
Oct 22, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Responsibilities:

As a member of Silicon Design methodology team, you will  

  • Methodology development and new methodology evaluations for Block level and Chip Level timing including, but not limited to constraints, budgeting, timing closure, data handoffs, margins, multi-scenario and timing-exceptions. 
  • Methodology development and new methodology evaluations for Block level and Chip Level EMIR, including but not limited to static/ dynamic EMIR drop analysis, Thermal aware EM analysis
  • Evaluate next generation methodologies related to STA, EMIR, 3DIC - SSIT,  AoA, CoWoS, etc.
  • Interface with various engineering groups, including Block design, CAD, software, and product engineering to guide design and analysis styles and review verification of blocks 
  • Develop/ enhance methodologies Timing / EMIR model generation and verification 
  • Debug design and flow issues related to Extraction, Noise, timing closure/ modeling/ constraint propgations, etc. 


Common Essentials Duties and Responsibilities include, but not limited to: 

  • Exercises solid analytical problem solving in troubleshooting component designs (e.g., timing analysis, constraint setting, EMIR) 
  • Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications in a timely manner 
  • Collaborates with design management and other engineering teams in identifying and addressing key areas where changes or the adaptation of methods is required to better align with Xilinx's needs
  • Specialist in technical innovation in the use of standard design implementation tools and methods (e.g. understands how to leverage the tool to have a positive impact on the design). 
  • Mentors junior design engineers on emerging methods and how best to integrate these into practice 

 

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Job Qualifications

  • BS with 5+ years of exp, MS with 3+ years of exp or PhD in Electrical Engineer, Computer Engineering or related equivalent
  • Basic knowledge of FPGA architecture
  • Experience in RTL, synthesis, place and route, static timing analysis (STA) and electrical analysis on ASIC/ CPU/ GPU or similar architectures
  • Fundamental static CMOS circuit design knowledge including simulation experience with Spice and Verilog
  • Experience with Primetime, Goldtime, Tempus and/or other STA tools etc.
  • Experience with Redhawk, Totem and/or other EMIR tools etc.
  • Experience with high frequency, low power, multi-voltage design techniques
  • Experience with automation using scripting techniques such as Perl, TCL, or Python
  • Strong debugging skills
  • Ability to develop clear and concise engineering documentation 
  • Excellent verbal and written communication and presentation skills
  • Excellent organizational skills and attention to detail
  • Leadership and mentorship skills
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