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XUP Engineering Intern

159125
Saggart, Co. Dublin, Ireland, Ireland
Oct 5, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

The Xilinx University Program (XUP), part of the office of the CTO (Chief Technology Officer) department, is seeking an intern with an interest in developing FPGA-based hardware and embedded software applications with Xilinx development tools to work in our group located in Dublin, Ireland.

This is an exciting position working on the latest FPGA hardware and software technologies from Xilinx, including the Zynq System-on-Chip and Zynq Ultrascale+ MPSOC, Vivado Design Suite, PYNQ framework, AWS F1 instances and Alveo data center boards using the Vitis Development Environment. 

 

Responsibilities may include:

  • Create and update XUP training materials, including labs, demos and application notes
  • Creating new example designs for FPGAs and for use with PYNQ
  • Supporting XUP physical and virtual events

Requirements:          

  • 3rd or 4th year Masters or Bachelors student in Electronic Engineering, or related Computer Science/Engineering degrees.
  • Good knowledge of digital circuit design including experience with VHDL/Verilog/HLS
  • Familiarity with Xilinx FPGA and system design tools including Vivado and Zynq
  • Excellent writing, communication, teamwork & problem-solving skills

 

Experience with PYNQ and Python would be an advantage.

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