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Description
This exciting position in the Xilinx IP Engineering group as the storage domain u-architect and lead designer will provide the individual with an opportunity to demonstrate strong technical leadership in Xilinx next generation data center storage IP offerings. Join us in delivering innovative IP solutions as we embark on our journey in providing world class storage solutions at more than 100Gbps line rate for Xilinx All Programmable FPGA platforms
As a Senior Design Engineer you will work as part of a team responsible for all phases of product development from definition to execution and Productization. Senior Design engineers are expected to participate in and lead all aspects of a technical project including: working closely with Product marketing managers, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization
This position requires the individual to be creative, team-oriented, technology savvy, able to u-architect and lead complex designs given a high level architecture and take complete responsibility for a quality delivery of the designs
Essential Functions:
A major part of your responsibility will be to take a lead technical role in all phases of the product development cycle from architecture through implementation, prototyping, validation and support including:
· Evaluating high level architecture to a implementation feasibility level
· Be the main liaison from the IP engineering team to the high speed IO design team and be the local high speed link design expert
· Contribute to new process improvement in design and development methodologies that impact the productivity
· Evaluating and executing design and development plans for IPs
· u-Architecture, design, documentation, prototyping
· Working with cross functional teams in reviewing the verification and validation plans and ensure the product delivered is of high quality
· Bachelors or Masters in Computer or Electrical/Electronics engineering
· Strong academic background
. A minimum of 8 years of relevant experience is required.
· Strong logic design concepts and computer design
· Expertise in Verilog, VHDL and exposure to industry simulators
· Expertise in front end RTL design flow steps like lint, CDC, STA etc
· Expertise in IP design