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At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
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Data Center Verification group at New Delhi Site is looking for Design Verification Engineer for FPGA block, sub-system and full chip verification. This is a fantastic opportunity for an Engineer with a passion for FPGA or ASIC development to join a growing team with access to world-class components and development infrastructure to work on all aspects of the FPGA development cycle. You'll be working in a team responsible for the functional verification of IP components and systems for use by the world’s leading hyperscalers, financial institutions and data science companies.
The individual will help develop Random Constrained Functional Coverage driven verification environments, at block, sub system and full chip level, to prove the functional correctness of FPGA SoCs.
The ideal candidate is one who has a proven track record on successful verification execution of high performance IPs and/or SoC designs. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the FPGA design teams with an eye towards improving overall product quality.
Skill & Experience:
Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES or Mentor Questa.
Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
Experience in full chip verification is a plus.
Requires experience in Perl, Python and/or other scripting language
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
Experience in modelling C++ and using C++ based models in verification is a plus.
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan) is a plus.
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality measurements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
Packet/wired-networking background, knowledge of Ethernet Layer 2/3,AXI and PCIe is a strong plus
Bachelor's Degree w/ 6+ years or MS w/ 4+ years in
Electrical/Electronics Engineering, Computer Engineering, or Computer Science.