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Principal Architect

158965
San Jose, CA, United States
Sep 4, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

 

 

Job Description

 

 

The Xilinx is looking for Senior Architect for the development of next generation ACAP (Adaptive Compute Acceleration Platform) devices. In this role, you will be responsible for the Chiplet technology and architecture development including Chiplet integration technology and Chip-to-Chip interconnect technology and architecture. You will develop novel technology and architecture solutions, write specifications, analyze PPA (performance, power and area) tradeoffs, and work with planning & development teams to architect best in class chiplet systems.

 

 

 

 

#mh

 

 

Job Qualifications

 

Role Requirements

  • Strong foundation in heterogenous multi-die systems integration  
  • Strong analytical problem solving, and attention to details
  • Experience in chiplets (multi-die) integration technologies  
  • Experience in chip-to-chip interconnects and packaging technology
  • Knowledge of silicon interposer and MCM best practices 
  • Knowledge of SoC, FPGA, and ML/AI Accelerators
  • Knowledge of programming languages such as C, Python
  • Excellent written and verbal interpersonal skills
  • Self-starter and great teammate 

 

 

Education and Years of Experience Requirements:

  • BS with 15+ years or MS with 12+ years or PhD with 8+ years with a degree in Electrical Engineering, Computer Engineering, or related field

 

 

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